BDEPEND=virtual/pkgconfig app-alternatives/ninja >=dev-build/cmake-3.20.5
DEFINED_PHASES=compile configure install prepare test
DEPEND=python_targets_python3_11? ( dev-lang/python:3.11 ) python_targets_python3_12? ( dev-lang/python:3.12 ) test? ( dev-python/psutil[python_targets_python3_11(-)?,python_targets_python3_12(-)?] sci-electronics/verilator ) sys-libs/ncurses:0=
DESCRIPTION=The fast free Verilog/SystemVerilog simulator
EAPI=8
HOMEPAGE=https://circt.llvm.org https://github.com/llvm/circt
IUSE=test python_targets_python3_11 python_targets_python3_12
KEYWORDS=~amd64 ~arm64 ~riscv ~x86
LICENSE=Apache-2.0-with-LLVM-exceptions UoI-NCSA BSD public-domain rc
RDEPEND=python_targets_python3_11? ( dev-lang/python:3.11 ) python_targets_python3_12? ( dev-lang/python:3.12 ) test? ( dev-python/psutil[python_targets_python3_11(-)?,python_targets_python3_12(-)?] sci-electronics/verilator ) sys-libs/ncurses:0=
REQUIRED_USE=|| ( python_targets_python3_11 python_targets_python3_12 )
RESTRICT=!test? ( test )
SLOT=0
SRC_URI=https://github.com/llvm/circt/archive/refs/tags/sifive/1\/14\/0.tar.gz -> circt-1.14.0.tar.gz https://github.com/llvm/llvm-project/archive/fe0f72d5c55a9b95c5564089e946e8f08112e995.tar.gz -> llvm-project-fe0f72d5c55a9b95c5564089e946e8f08112e995.tar.gz
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_md5_=03a8a123dba4383e1af301a8414087de