BDEPEND=>=dev-vcs/git-1.8.2.1[curl]
DEFINED_PHASES=compile install unpack
DEPEND=dev-vcs/git media-gfx/xdot dev-libs/boost dev-lang/tcl
DESCRIPTION=framework for Verilog RTL synthesis
EAPI=8
HOMEPAGE=http://www.clifford.at/yosys/
INHERIT=git-r3
LICENSE=ISC
PROPERTIES=live
SLOT=0
_eclasses_=git-r3	875eb471682d3e1f18da124be97dcc81
_md5_=7e596597b1d987fdfaec275bdae7806f