BDEPEND=>=dev-vcs/git-1.8.2.1[curl]
DEFINED_PHASES=compile configure install prepare unpack
DEPEND=dev-vcs/git media-gfx/xdot dev-libs/boost sys-devel/clang
DESCRIPTION=framework for Verilog RTL synthesis
EAPI=8
HOMEPAGE=http://www.clifford.at/yosys/
INHERIT=git-r3
LICENSE=ISC
PROPERTIES=live
SLOT=0
SRC_URI=https://github.com/YosysHQ/abc/archive/bb64142b07794ee685494564471e67365a093710.tar.gz -> abc-bb64142b07794ee685494564471e67365a093710.tar.gz
_eclasses_=git-r3	fbb2889c81f3a05910c1524db69425c1
_md5_=158bb2afa140131adcfe2c0cb05589eb